Post-Silicon Validation Engineering Intern - Characterization and Support
Cadence Design Systems · Hardware
- Location
- San Jose, CA
- Metro
- San Francisco Bay Area
- Workplace
- On-site
- Level
- Intern
- Type
- Internship
- Pay
- $40–$69/hr (estimated from posting text)
- Posted
- 2 months ago
- Source
- Simplify internships list
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What the posting covers
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. (local candidates will be considered) Intern will be responsible for validating both system-level and electrical…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The annual salary range for California is $40/hr to $69/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as…
Excerpts only. The employer’s page has the complete posting.